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  1. JDK
  2. JDK-8154943

AArch64: redundant address computation instructions with vectorization

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    Details

    • Type: Bug
    • Status: Resolved
    • Priority: P4
    • Resolution: Fixed
    • Affects Version/s: 9
    • Fix Version/s: 9
    • Component/s: hotspot
    • Labels:
      None
    • Subcomponent:
    • Resolved In Build:
      b120
    • CPU:
      aarch64

      Description

      Example generated code:

       ;; B106: # B106 B107 <- B105 B106 Loop: B106-B106 inner main of N612 Freq: 293550

        0x000003ffa9275650: sbfiz x0, x4, #3, #32
        0x000003ffa9275654: add x3, x5, x0
        0x000003ffa9275658: sbfiz x7, x4, #3, #32
        0x000003ffa927565c: ldr q19, [x3,#16]
        0x000003ffa9275660: add x19, x5, x7
        0x000003ffa9275664: ldr q20, [x19,#32] ;*daload {reexecute=0 rethrow=0 return_oop=0}
                                                      ; - jnt.scimark2.LU::factor@237 (line 235)

      both sbfiz and add are strictly indentical and so fully redundant. The redundant instructions are caused by 2 ConvI2L nodes that are identical except for their type:

      1984 ConvI2L _ 1683 [ 1987 ] debug_idx = 33701984 type = long: dump_spec = #long:minint..maxint-1:www
      1678 ConvI2L _ 1683 [ 1672 ] bci = 49 debug_orig = dump_spec = #long:0..maxint-1:www debug_idx = 30401678 line = 183 type = long:

      The type doesn't help code generation on arm so it could be widened and duplicated instructions could then be removed.

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              Assignee:
              roland Roland Westrelin
              Reporter:
              roland Roland Westrelin
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                Updated:
                Resolved: