P4
The AArch64 backend generates oop literals as 48-bit constants as currently the address space size for Aarch64 is usually 48-bits.
As it is RISC, a number of instructions are used to do this:
mov x2, 0x3210
movk x2, 0x7654, LSL #16
movk x2, 0xba98, LSL #32
This puts 0x0000ba9876543210 into register x2.
However, in ZGC we are putting the pointer coloured bits into the top 4 bits, which requires these bits to be preserved when stored in oops.
We can conditionally add an extra instruction:
movk x2, 0xfcdb, LSL #48
There are two options, do this for all literal addresses, or only for addresses to OOPs.
Later revisions of the ArmV8 architecture support 52-bit virtual addresses. This enhancement will go some way to supporting that.
As it is RISC, a number of instructions are used to do this:
mov x2, 0x3210
movk x2, 0x7654, LSL #16
movk x2, 0xba98, LSL #32
This puts 0x0000ba9876543210 into register x2.
However, in ZGC we are putting the pointer coloured bits into the top 4 bits, which requires these bits to be preserved when stored in oops.
We can conditionally add an extra instruction:
movk x2, 0xfcdb, LSL #48
There are two options, do this for all literal addresses, or only for addresses to OOPs.
Later revisions of the ArmV8 architecture support 52-bit virtual addresses. This enhancement will go some way to supporting that.