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  1. JDK
  2. JDK-8260025

Missing comma in VM_Version_Ext::_family_id_amd

    Details

    • Type: Bug
    • Status: Resolved
    • Priority: P4
    • Resolution: Fixed
    • Affects Version/s: 11, 15, 17
    • Fix Version/s: 17
    • Component/s: hotspot
    • Labels:
      None
    • Subcomponent:
    • Resolved In Build:
      b07
    • CPU:
      x86_64

      Description

      HotSpot cannot identify Zen (family 17h) processor. You can see this problem in flight record as below:

      ```
      java -XX:StartFlightRecording=filename=test.jfr --version
      ```

      `(null)` in `cpu` and `<unknown>` in `Family` should be `Zen`.

      ```
      $ jfr print --events jdk.CPUInformation test.jfr
      jdk.CPUInformation {
        startTime = 15:59:37.207
        cpu = "AMD (null) (HT) SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 SSE4A AMD64"
        description = "Brand: AMD Ryzen 3 3300X 4-Core Processor , Vendor: AuthenticAMD
      Family: <unknown> (0x17), Model: <unknown> (0x71), Stepping: 0x0
      Ext. family: 0x8, Ext. model: 0x7, Type: 0x0, Signature: 0x00870f10
      Features: ebx: 0x00020800, ecx: 0xfed83203, edx: 0x178bfbff
      Ext. features: eax: 0x00870f10, ebx: 0x20000000, ecx: 0x004003f3, edx: 0x2fd3fbff
      Supports: On-Chip FPU, Virtual Mode Extensions, Debugging Extensions, Page Size Extensions, Time Stamp Counter, Model Specific Registers, Physical Address Extension, Machine Check Exceptions, CMPXCHG8B Instruction, On-Chip APIC, Fast System Call, Memory Type Range Registers, Page Global Enable, Machine Check Architecture, Conditional Mov Instruction, Page Attribute Table, 36-bit Page Size Extension, CLFLUSH Instruction, Intel Architecture MMX Technology, Fast Float Point Save and Restore, Streaming SIMD extensions, Streaming SIMD extensions 2, Hyper Threading, Streaming SIMD Extensions 3, PCLMULQDQ, Supplemental Streaming SIMD Extensions 3, Fused Multiply-Add, CMPXCHG16B, Streaming SIMD extensions 4.1, Streaming SIMD extensions 4.2, MOVBE, Popcount instruction, AESNI, XSAVE, OSXSAVE, AVX, F16C, LAHF/SAHF instruction support, Core multi-processor leagacy mode, Advanced Bit Manipulations: LZCNT, SSE4A: MOVNTSS, MOVNTSD, EXTRQ, INSERTQ, Misaligned SSE mode, SYSCALL/SYSRET, Execute Disable Bit, RDTSCP, Intel 64 Architecture"
        sockets = 1
        cores = 2
        hwThreads = 2
      }
      ```

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              • Assignee:
                ysuenaga Yasumasa Suenaga
                Reporter:
                ysuenaga Yasumasa Suenaga
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                Dates

                • Created:
                  Updated:
                  Resolved: